This functional block is a General Purpose Input/Output core with 8 input/output ports via a serial SPI interface. The core is able to generate separate interrupts for each input. The usage of a pin can be set in a GPIO Direction Register. Two Interrupt Enable Registers give the possibility to set the edge of the input signal (rising, falling or both) which shall generate an interrupt. The state of the GPIO input pins can be read with the Port State Register.
MEN IP cores are described in standard VHDL language and the standard Wishbone bus is used as the system interface.
By using IP cores, application-specific functions can be performed flexibly and individually in the FPGA on a growing range of MEN CPU boards. These IP cores can be assembled from the MEN function library and reconfigured, combined with IP cores from other providers or even completely redeveloped as required. The FPGA behaves just like a standard PCI component. The FPGA functions are loaded by software when the system is booted and are available in less than 1 s. On PowerPC® platforms the FPGA can be dynamically updated during operation. On Pentium® platforms FPGA updates are also possible in the boot Flash during operation and are then available once the system is rebooted.
Logic elements (Altera® Cyclone® device family): 120 typ.
Pin count: 4
Wishbone bus interface compliant with Wishbone Specification B.3
8-bit data transfer, 66MHz bus frequency
Supported Wishbone bus cycles
Up to 8 general purpose input/output ports
Interrupt on input signal change (rising and/or falling edge)
Separate programmable interrupts for each input
Generics for all register values
This product is designed to work under Linux. See below for potentially available separate software packages from MEN.