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Rugged Computer Boards and Systems for
Harsh, Mobile and Mission-Critical Environments
Harsh, Mobile and Mission-Critical Environments
16Z045_FLASH - Flash Interface IP Core
Overview
Diagram
Main Features
- FPGA IP Core
- Controls standard Flash devices
- Wishbone bus interface
Description
The Flash Interface 16Z045_FLASH is used to connect standard Flash devices to the Wishbone bus via read-only and read/write addressing. The Flash memory can be used to store FPGA configuration images or software applications. Flash memory contents can be updated by software (e.g. using the MEN tool FPGA_LOAD) in PCI or M-Module™ systems. If the Flash is used to store FPGA configuration images, an external circuit reads the FPGA configuration during power-up in less than 1s. In addition, it is possible to update the FPGA dynamically during operation. Nios® soft processors can boot from Flash memory using the 16Z045_FLASH Flash Interface.
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Technical Data
Size
Logic elements (Altera® Cyclone® device family): 80 typ.
Pin count min: 32
Pin count max: 73
System-Bus Interface
Wishbone bus interface compliant with Wishbone Specification B.3
32-bit data transfer, 33/66MHz bus frequency
Supported Wishbone bus cycles
•
Single read/write
Functionality
Flash interface
Standard Flash interface timing
Up to 29 address bits
8 or 16 data bits (32 bits possible, but not yet tested in hardware)
16 MB memory size support
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