The Flash Interface 16Z045_FLASH is used to connect standard Flash devices to the Wishbone bus via read-only and read/write addressing. The Flash memory can be used to store FPGA configuration images or software applications. Flash memory contents can be updated by software (e.g. using the MEN tool FPGA_LOAD) in PCI or M-Module™ systems. If the Flash is used to store FPGA configuration images, an external circuit reads the FPGA configuration during power-up in less than 1s. In addition, it is possible to update the FPGA dynamically during operation. Nios® soft processors can boot from Flash memory using the 16Z045_FLASH Flash Interface.
MEN IP cores are described in standard VHDL language and the standard Wishbone bus is used as the system interface.
By using IP cores, application-specific functions can be performed flexibly and individually in the FPGA on a growing range of MEN CPU boards. These IP cores can be assembled from the MEN function library and reconfigured, combined with IP cores from other providers or even completely redeveloped as required.
Logic elements (Altera® Cyclone® device family): 80 typ.
Pin count min: 32
Pin count max: 73
Wishbone bus interface compliant with Wishbone Specification B.3
32-bit data transfer, 33/66MHz bus frequency
Supported Wishbone bus cycles
Standard Flash interface timing
Up to 29 address bits
8 or 16 data bits (32 bits possible, but not yet tested in hardware)