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Rugged Computer Boards and Systems for
Harsh, Mobile and Mission-Critical Environments
Harsh, Mobile and Mission-Critical Environments
16Z069_RST - Reset Controller IP Core
Overview
Diagram
Main Features
- FPGA IP Core
- Suited for every FPGA design
- Wishbone bus interface
Description
The reset controller provides a power up reset output and is therefore intended to be used in every FPGA design. It also provides up to 24 reset inputs (32 in earlier revisions) and one reset output, a 500 Hz and a 64 kHz clock output and a simple watchdog with programmable timeout and dedicated reset output. Furthermore, revisions 7 and later feature 8 dedicated inputs for PLL lock signals that can optionally be used as reset inputs. The reset pulse width of the controller can be pre-determined.
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Technical Data
Size
Logic elements (Altera® Cyclone® device family): 204 typ.
Pin count: depends on number of external resets
System-Bus Interface
Wishbone bus interface compliant with Wishbone Specification B.3
32-bit data transfer, up to 66MHz bus frequency
Supported Wishbone bus cycles
•
Single read/write
Avalon® bus interface compliant with Avalon® Bus Specification
32-bit data transfer, up to 66MHz bus frequency
Supported Avalon® bus cycles
•
Single read/write
Functionality
Reset Inputs/Outputs
•
Up to 24 reset inputs (32 for revisions 6 and earlier)
•
8 dedicated inputs for PLL lock signals (revisions 7 and later, optionally used as reset inputs)
•
One reset controller reset output (generated using the reset inputs)
•
One power up reset output
•
One watchdog controlled reset output
•
One PLL lock lost output
Clock Outputs
•
One 500 Hz clock
•
One 64 kHz clock
Clock Inputs
•
One clock from a crystal oscillator for the PLL lock monitor
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