This IP core is an IDE controller which uses an external NAND Flash for storage. This module is intended for hardware boards where a CompactFlash® card would need too much board space. It is based on the Nios® II soft core processor from Altera® and includes several additional modules.
MEN IP cores are described in standard VHDL language and the standard Wishbone bus is used as the system interface.
By using IP cores, application-specific functions can be performed flexibly and individually in the FPGA on a growing range of MEN CPU boards. These IP cores can be assembled from the MEN function library and reconfigured, combined with IP cores from other providers or even completely redeveloped as required. The FPGA behaves just like a standard PCI component. The FPGA functions are loaded by software when the system is booted and are available in less than 1 s. On PowerPC® platforms the FPGA can be dynamically updated during operation. On Pentium® platforms FPGA updates are also possible in the boot Flash during operation and are then available once the system is rebooted.
Logic elements (Altera® Cyclone® device family): 4200 typ.
Pin count: 14
RAM: 29 x 4096 bits
Wishbone bus interface compliant with Wishbone Specification B.3
32-bit data transfer, up to 133MHz bus frequency
Supported Wishbone bus cycles
Avalon® bus interface compliant with Avalon® Bus Specification
32-bit data transfer, 33/66MHz bus frequency
Supported Avalon® bus cycles