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Tailored I/O functions realized as IP cores for configuration in onboard FPGAs The UART controller IP core includes up to four 16550D compatible universal asynchronous receiver transmitter modules.

16Z125_UART - UART Controller IP Core

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Diagram
16Z125_UART Diagram

Larger picture of 16Z125_UART Diagram

Main Features
  • FPGA IP Core
  • Up to four independent UART channels
  • Compatible to 16550 UART
  • Up to 3 Mbit/s data rate
  • Wishbone bus interface
Description Open

The UART controller includes up to four 16550D compatible universal asynchronous receiver transmitter modules. The four channels of the quad UART are independent of each other and offer a data rate of up to 3 Mbit/s. Each UART contains two FIFOs, one for transmitting and one for receiving data. Each FIFO has the extended size of 60 bytes. The eight FIFOs used in the four UARTs are combined in an internal RAM, an arbiter arbitrates the accesses of the four UART modules and the CPU interface. The Wishbone bus is used as the CPU interface.

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Technical Data

Size

Quad UART
• Logic elements (Altera® Cyclone® device family): 1800 typ.
• Pin count min: 8 (4 receive lines and 4 transmit lines)
• Pin count max: 36

Triple UART
• Logic elements (Altera® Cyclone® device family): 1300 typ.
• Pin count min: 6 (3 receive lines and 3 transmit lines)
• Pin count max: 27

Dual UART
• Logic elements (Altera® Cyclone® device family): 1000 typ.
• Pin count min: 4 (2 receive lines and 2 transmit lines)
• Pin count max: 18

Single UART
• Logic elements (Altera® Cyclone® device family): 700 typ.
• Pin count min: 2 (1 receive line and 1 transmit line)
• Pin count max: 9

RAM: 1 x M4K (Cyclone® I and II) or 1 x M9K (Cyclone® III)

(2x M4K (Cyclone® I and II) or 1 x M9K (Cyclone® III) for 124-byte buffer)

System-Bus Interface

Wishbone bus interface compliant with Wishbone Specification B.3

32-bit data transfer, 33MHz or 66MHz bus frequency

Supported Wishbone bus cycles
• Single read/write

UART Functionality

Quad UART

16550D compatible

RS232 or RS422/RS485 mode (switchable by software)

Full or half-duplex (switchable by software)

Data rates up to 3Mbit/s

60-byte transmit/receive buffer (124-byte buffer on request)

Handshake lines: CTS, RTS; DCD, DSR, DTR; RI; full support, reduced handshake for lower pin count

Automatic RTS/CTS flow control for RS232 on request

Software
Article No. Description More
Linux
LinuxThis product is designed to work under Linux. See below for potentially available separate software packages from MEN.
13Z025-90Linux native driver (MEN) for 16Z025_UART, 16Z057_UART and 16Z125_UART Download
Details
VxWorks
Wind RiverThis product is designed to work under VxWorks®. For details regarding supported/unsupported board functions please refer to the corresponding software data sheets.
13Z025-60VxWorks® native driver (MEN) for 16Z025_UART, 16Z057_UART and 16Z125_UART Download
Details
QNX
QNX®This product is designed to work under QNX®. For details regarding supported/unsupported board functions please refer to the corresponding software data sheets.
13Z025-40QNX® 6.3 native driver (MEN) for 16Z025_UART and 16Z125_UART Download
Details
13Z025-41QNX® 6.4 native driver (MEN) for 16Z025_UART and 16Z125_UART Download
Details
13Z025-42QNX® 6.5 native driver (MEN) for 16Z025_UART and 16Z125_UART Download
Details

For operating systems not mentioned here contact MEN sales.

Documentation
Article No. Description More
16Z125-DS16Z125_UART Data Sheet (PDF) Download
22Z125-ER16Z125_UART Errata (PDF) Download
22Z125-0016Z125_UART Reference Manual (PDF) Download
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