10PP01-60 VxWorks® 5.4..5.5 BSP for PP1

Revision History

-----[ BSP_1_2_24 ]-----
[ 2006-03-09 13:30:35 by UFRANKE ]
BSP 1.24
 fixed
  - USB init looks for MPC5200B_PCI_DEVICE_ID also

-----[ BSP_1_2_23 ]-----
[ 2006-03-01 11:48:54 by UFRANKE ]
BSP 1/2.23
 added
  + FRAM precharge timing woraround
  + INCLUDE_POSIX_PTHREADS
  + INCLUDE_POSIX_TIMERS
  + IIC glitch filter register setup for MPC5200B
  + sysgetSvr/Pvr()
 changed
  - updated ethernet to BESTCOMM 2.2
  - enabled PPC603 core dynamic power management
  - enable pipelining on XLB
  - cache coherency protocol for SDRAM
 fixed
  - raw FLASH device was not initialized
    if booted from MENMON second edition
  - i28f000.c problem if knownSize < chipSize
    resetAll takes no effect after writing to flash

-----[ BSP_1_2_22 ]-----
[ 2006-01-26 11:25:00 by UFRANKE ]
BSP 1.22
 added
  + MPC5200 B support
  + non SCPCI PCI access (MPC5200 Rev B2)
  + external USB clock   (MPC5200 Rev B2)
  + sysGetSvr(), sysGetPvr()
  + MENMON hurricane support nspeed0= for network speed setting
  + mpc5200FecEnd displays VxWorks version compiled for
  + __build_env.txt__ for build environment informations
  + auxClk for spy
  + sysPrepareMpc5200Mscan() setups PSC2 pins for CAN
 fixed
  - workaround for PCI config access behind a bridge
    Errata 435 of MPC5200 Rev A
  - pt_canexp.c MSCAN_CTL1 enables IPB clock for MPC5200 B3
  - mgt5200Sio.c check IMR register so only real TX interrupts are handled
  - pp01_cfg.h PP01CFG_PCI_IRQ_INTA from 20 to 0x20
  - ren MENP01FLASH_DevRemove to MENPP01FLASH_DevRemove
  - full duplex mode flag
    get it from phyMode put into phyFlags
    if BSP specific auto negotiation routine
 changed
  - get SIO, aux clock, ethernet, IRQ driver from DRIVERS path
    not longer BSP specific
  - support 128MB RAM
  - MMU disabled memory coherency multi processor support
  - wdog_cfg.c define STANDALONE to STANDARD

-----[ BSP_1_2_21 ]-----
[ 2004-09-21 11:42:49 by ufranke ]
Initial Revision

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