P598 - Conduction-Cooled USM™ Main PMC

FPGA

Flexible Configuration

This MEN board offers the possibility to add customized I/O functionality in FPGA.

It depends on the board type, pin counts and number of logic elements which IP cores make sense and/or can be implemented. Please contact MEN for information on feasibility.

You can find more information on our web page "User I/O in FPGA"

FPGA Capabilities

FPGA Altera® Cyclone® II EP2C35
• 33,216 logic elements
• 483,840 total RAM bits
• Supports Nios® II soft processor

Connection
• Functions can be linked to Wishbone or Avalon® bus
• Available pin count: 46 pins (FPGA to USM™)
• Functions available via USM™ at rear I/O connector

MEN offers an FPGA Development Package as well as Flash update tools for different operating systems.
• Package comes with function-identical convection-cooled PMC module with front I/O
• Only for development of FPGA, independent of conduction cooling

MEN IP Cores

MEN offers a large number of standard IP cores.

Examples:
• IDE (e.g. PIO mode 0, UDMA mode 5)
• UARTs
• CAN bus
• Display control
• Fast Ethernet (10/100Base-T)
• ...

For IP cores developed by MEN please refer to our IP core overview.
• IP Core compare chart (PDF)

MEN also offers development of new (customized) IP cores.

Third-Party IP Cores

Third-party IP cores can also be used in combination with MEN IP cores.

Examples:
• www.altera.com
• www.opencores.org

FPGA Design Environment

Altera® offers free download of Quartus® II Web Edition
• Complete environment for FPGA and CPLD design
• Includes schematic- and text-based design entry
• Integrated VHDL and Verilog HDL synthesis and support for third-party synthesis software
• SOPC Builder system generation software
• Place-and-route, verification, and programming

» Altera® Quartus® II Web Edition FPGA design tool

FPGA Packages