This counter is compatible with the 82C54 programmable Interval Timer Chip. It is recommended to read the datasheet of the 82C54 in order to fully understand the requirements and to see all the programming examples. The IP core is included into a timer counter unit, which includes clock input switching, interrupt logic and a programmable time base. The timer/counter unit provides three 8254 chips, so 9 counters can be used. Every individual part of the timer/counter unit has a Wishbone interface, so it can be used as a stand-alone module.
MEN IP cores are described in standard VHDL language and the standard Wishbone bus is used as the system interface.
By using IP cores, application-specific functions can be performed flexibly and individually in the FPGA on a growing range of MEN CPU boards. These IP cores can be assembled from the MEN function library and reconfigured, combined with IP cores from other providers or even completely redeveloped as required. The FPGA behaves just like a standard PCI component. The FPGA functions are loaded by software when the system is booted and are available in less than 1 s. On PowerPC® platforms the FPGA can be dynamically updated during operation. On Pentium® platforms FPGA updates are also possible in the boot Flash during operation and are then available once the system is rebooted.
Logic elements typ.: 3300 typ.
Pin count min: 3
Pin count max: 9
Wishbone bus interface compliant with Wishbone Specification B.3
32-bit data transfer, 33MHz bus frequency
Supported Wishbone bus cycles