This module generates up to 16 PWM signals. The period and pulse can be configured independently for each PWM channel.
MEN IP cores are described in standard VHDL language and the standard Wishbone bus is used as the system interface.
By using IP cores, application-specific functions can be performed flexibly and individually in the FPGA on a growing range of MEN CPU boards. These IP cores can be assembled from the MEN function library and reconfigured, combined with IP cores from other providers or even completely redeveloped as required. The FPGA behaves just like a standard PCI component. The FPGA functions are loaded by software when the system is booted and are available in less than 1 s. On PowerPC® platforms the FPGA can be dynamically updated during operation. On Pentium® platforms FPGA updates are also possible in the boot Flash during operation and are then available once the system is rebooted.
Logic elements (Altera® Cyclone® device family): min. 80
Pin count min: 1
Pin count max: 15
Wishbone bus interface compliant with Wishbone Specification B.3
32-bit data transfer, 33MHz bus frequency
Supported Wishbone bus cycles
Pulse width modulation
Up to 16 PWM signals
Independent period and pulse configuration
This product is designed to work under Linux. See below for potentially available separate software packages from MEN.