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P506 - Quad CAN Bus Interface PMC
FPGA
Flexible Configuration
This MEN board offers the possibility to add customized I/O functionality in FPGA.
It depends on the board type, pin counts and number of logic elements which IP cores make sense and/or can be implemented. Please contact MEN for information on feasibility.
You can find more information on our web page "User I/O in FPGA"
FPGA Capabilities
FPGA Altera® Cyclone® II EP2C35
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33,216 logic elements
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483,840 total RAM bits
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Supports Nios® II soft processor
Connection
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Functions can be linked to Wishbone or Avalon® bus
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Available pin count: 46 pins (FPGA to USM™)
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Functions available via USM™ at front I/O connector
