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F50P - Embedded Single Board Computer with QorIQ MPC8548
3U CompactPCI PlusIO
The F50P is a low-power PowerPC based embedded computer for industrial automation and railway transportation, featuring a PowerQUICC P3 processor. The SBC is compliant with the PICMG 2.30 standard and as such a perfect migration path from CompactPCI to CompactPCI Serial.
F50P 3U CompactPCI PlusIO PowerPC MPC8548 CPU Board
F50P front view
F50P with heat sink
F50P with heat sink
Main Features
- 32-bit CompactPCI and PICMG 2.30 PlusIO
- 8 HP or 12 HP with front I/O
- MPC8548 (or MPC8543), up to 1.5 GHz
- Up to 2 GB (ECC) DDR2 SDRAM
- Up to 128 KB FRAM, 2 MB SRAM
- Up to 16 GB SSD Flash
- Standard front I/O: 2 Gb Ethernet, 2 USB
- Standard rear I/O: 4 USB, 2 SATA
- FPGA for user-defined I/O functions (option)
- MENMON BIOS for PowerPC cards
- -40°C to +70°C (8 HP) (screened)
Technical Data
- 800 MHz up to 1.5 GHz
- Please see Standard Configurations for available standard versions.
- e500 PowerPC core with MMU and double-precision embedded scalar and vector floating-point APU
- Integrated Northbridge and Southbridge
- 2 x 32 KB L1 data and instruction cache, 512 KB / 256 KB L2 cache integrated in MPC8548/MPC8543
- Up to 2 GB SDRAM system memory
- Soldered
- DDR2 with or without ECC
- Up to 300 MHz memory bus frequency, depending on CPU
- Up to 16 GB soldered Flash disk (SSD solid state disk)
- Up to 32 MB additional DDR2 SDRAM, FPGA-controlled, e.g. for video data
- 16 MB boot Flash
- 2 MB non-volatile SRAM
- With GoldCap backup
- 128 KB non-volatile FRAM
- Serial EEPROM 4 kbits for factory settings
- Parallel IDE (PATA)
- Up to 16 GB soldered ATA Flash disk (SSD solid state disk)
- Serial ATA (SATA)
- Up to two ports via rear I/O J2
- Transfer rates up to 150 MB/s (1.5 Gbit/s)
- Via PCI-to-SATA bridge
- See interface configuration matrix showing possible I/O combinations (PDF)
- FPGA-controlled (optional)
- VGA connector prepared at front panel
- USB (host)
- Five USB 2.0 host ports
- One Type A connector at front panel
- Four ports via rear I/O J2
- OHCI and EHCI implementation
- Data rates up to 480 Mbit/s
- USB (client)
- One USB client port on Type A connector at front panel
- Via UART-to-USB converter
- Data rates up to 115.2 kbit/s
- 16-byte transmit/receive buffer
- Handshake lines: none
- Ethernet
- Up to three 10/100/1000Base-T Ethernet channels with MPC8548/E (two channels with MPC8543/E)
- Two RJ45 connectors at front panel
- Two front-panel LEDs for channels for LAN link, activity status and connection speed
- All three possible also via rear I/O J2 (Note: requires additional Ethernet transformers on rear I/O board or backplane.)
- See interface configuration matrix showing possible I/O combinations (PDF)
- User-defined I/O
- FPGA-controlled (optional)
- Up to 64 I/O lines
- Connection via rear I/O J2
- See interface configuration matrix showing possible I/O combinations (PDF)
- One USB 2.0 host (Type A)
- One USB client (Type A)
- Two Ethernet (RJ45)
- Four USB 2.0
- Up to three 1000Base-T Ethernet
- Up to two SATA
- Up to 64 I/O lines with optional FPGA
- Reduces Ethernet/SATA interfaces
- See interface configuration matrix showing possible I/O combinations (PDF)
- Standard version compatible with PICMG 2.30 CompactPCI PlusIO
- Two SATA
- Four USB 2.0
- 1PCI33/0PCIE/2SATA1.5/4USB2/0ETH
- The FPGA offers the possibility to add customized I/O functionality. See Options
- Standard: FPGA not assembled
- Real-time clock with GoldCap backup
- Temperature sensor, power supervision and watchdog
- Status LED at the front
- Reset button
- Compliance with CompactPCI Core Specification PICMG 2.0 R3.0
- System slot
- 32-bit/32-MHz PCIe-to-PCI bridge
- V(I/O): +3.3 V (+5 V tolerant)
- Board can be supplied with +5 V, +3.3 V and +12 V from backplane, all other voltages are generated on the board
- Backplane J1 connector used only for power supply
- +5 V (-3%/+5%), 800 mA approx.
- +3.3 V (-3%/+5%), 350 mA approx.
- ±12 V (-5%/+5%), 1 A approx.
- Dimensions: conforming to CompactPCI specification for 3U boards
- Front panel:
- 8 HP without FPGA
- 12 HP with FPGA
- Weight: 626 g
- Temperature range (operation):
- -40..+70°C
- 0..+60°C (with 16 GB SSD Flash disk)
- Airflow: min. 1.0 m/s
- Conduction cooled variety F50C also available
- Temperature range (storage): -40..+85°C
- Relative humidity (operation): max. 95% non-condensing
- Relative humidity (storage): max. 95% non-condensing
- Altitude: -300 m to + 3,000 m
- Shock: 15 g, 11 ms
- Bump: 10 g, 16 ms
- Vibration (sinusoidal): 1 g, 10..150 Hz
- Linux
- VxWorks
- QNX (on request; support of the FPU is currently not provided by QNX)
- INTEGRITY (Green Hills Software) support available. Please contact Green Hills for further information.
- OS-9 (on request)
- For more information on supported operating system versions and drivers see Software.
Options
- Several PowerQUICC III types with different clock frequencies
- MPC8548 or MPC8548E
- 1 GHz, 1.2 GHz, 1.33 GHz or 1.5 GHz
- MPC8543 or MPC8543E
- 800 MHz or 1 GHz
- System RAM
- 512 MB, 1 GB or 2 GB
- With or without ECC
- Flash Disk
- 2 GB, 4 GB, 8 GB or 16 GB
- Please note that the 16 GB Flash disk component only supports a temperature range of 0..+60°C!
- FRAM
- 0 KB or 128 KB
- Additional SDRAM
- 0 MB or 32 MB
- With optional FPGA
- See interface configuration matrix showing possible I/O combinations (PDF)
- VGA at front (with optional FPGA)
- Ethernet
- Up to two channels at front
- Up to three channels at rear
- Only two channels total with MPC8543
- SATA
- Up to two channels at rear
- Up to 64 user-defined I/O lines
- With optional FPGA, see below
- Reduces number of Ethernet/SATA channels
- The optional onboard FPGA offers the possibility to implement customized I/O functionality.
- FPGA Altera Arria GX AGX35C
- 33,520 logic elements
- 1,348,416 total memory bits
- Connected to CPU via PCI Express x1 link
- Connection
- Available pin count: 64 pins
- Functions available via rear I/O J2 connector
- Please note that the FPGA expands the board's width by 4 HP, to 12 HP!
- You can find more information under 'FPGA Design'
- -40..+70°C on 8 HP with heat sink (without FPGA) for convection cooling
- Conduction cooled variety F50C also available, for -40..+85°C
Ordering Information
MPC8548, 1.33 GHz, 2 GB SSD Flash, 512 MB DDR2 RAM, 2 MB SRAM, 128 KB FRAM, front I/O and PICMG 2.30 rear I/O (2 SATA, 4 USB), 8 HP, no FPGA, -40..+70°C screened
This product can be ordered until 2018-01-313U CompactPCI, MPC8543, FPGA rear I/O, 800 MHz, -40..+85°C
This product can be ordered until 2018-01-31
CompactPCI PlusIO rear transition module 3U/80mm, 2 Ethernet, 4 USB, 4 SATA, 4 PCIe x1, -40°C..+85°C qualified
Details
CompactPCI 19" 4U/84HP rack-mount enclosure for 3U cards (vertical), 4+4-slot 3U CompactPCI / CompactPCI Serial hybrid backplane, prepared for rear I/O, 250W power supply wide range 90..264VAC on rear, 1U fan tray with 2 fans included, 0..+60°C
DetailsMEN delivers turn-key systems completely installed (hardware, operating system, accessories), wired and tested. Different rack sizes, power supplies and backplanes on request.
For details please contact your local sales representative.
Software
Linux General Linux BSP for A17, EM9, EM9A, EK9, F50C, F50P and XM50
VxWorks VxWorks 6.4/6.5 BSP (MEN) for A17, EK9, EM9, EM9A, F50C, F50P and XM50
VxWorks 6.9 BSP (MEN) for A17, EK9, EM9, EM9A, F50C, F50P and XM50
INTEGRITY This product is designed to work under the INTEGRITY RTOS from Green Hills Software. An INTEGRITY Board Support Package for this board is provided by Green Hills Software. For more information and product support please contact Green Hills Software (www.ghs.com).
MENMON (Firmware) for XM50, F50C and F50P (object code)
A Windows USB2UART driver from FTDI is available for XM50, XM51 and F50P/F50C Windows hosts.
More info & downloads