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16Z025_UART - UART Controller

FPGA IP Core

The 16Z025_UART is a UART controller IP core which includes up to four 16550D compatible universal asynchronous receiver transmitter modules.

Download data sheet

Main Features

  • FPGA IP Core
  • Up to four independent UART channels
  • Compatible to 16550 UART
  • Wishbone bus interface
16Z025_UART Product Image

Technical Data

Size
  • Quad UART
    • Logic elements (Altera Cyclone device family): 1800 typ.
    • Pin count min: 9
    • Pin count max: 33
  • Triple UART
    • Logic elements (Altera Cyclone device family): 1300 typ.
    • Pin count min: 7
    • Pin count max: 25
  • Dual UART
    • Logic elements (Altera Cyclone device family): 1000 typ.
    • Pin count min: 5
    • Pin count max: 17
  • Single UART
    • Logic elements (Altera Cyclone device family): 700 typ.
    • Pin count min: 3
    • Pin count max: 9
  • RAM: 1 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
UART Functionality
  • Quad UART
  • 16550D compatible
  • Data rates up to 115.2kbit/s
  • 60-byte transmit/receive buffer
  • Handshake lines: CTS, RTS; DCD, DSR, DTR; RI; full support, reduced handshake for lower pin count

Software

Linux
13MD05-90

MDIS5 System (and Device Driver) Package (MEN) for Linux. This software package includes most standard device drivers available from MEN.

13Z025-90

Linux native driver (MEN) for 16Z025_UART, 16Z057_UART and 16Z125_UART

VxWorks
13Z025-60

VxWorks native driver (MEN) for 16Z025_UART, 16Z057_UART and 16Z125_UART

QNX
13Z025-40

QNX 6.3 native driver (MEN) for 16Z025_UART and 16Z125_UART

13Z025-41

QNX 6.4 native driver (MEN) for 16Z025_UART and 16Z125_UART

13Z025-42

QNX 6.5 native driver (MEN) for 16Z025_UART and 16Z125_UART

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