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16Z037_GPIO - GPIO Controller with Serial Interface

FPGA IP Core

This functional block is a General Purpose Input/Output core with 8 input/output ports via a serial SPI interface.

Download data sheet

Main Features

  • FPGA IP Core
  • 8 input/output ports via serial SPI interface
  • Separate programmable interrupts for each input
  • Wishbone bus interface
16Z037_GPIO Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 120 typ.
  • Pin count: 4
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 8-bit data transfer, 66MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
GPIO Functionality
  • Up to 8 general purpose input/output ports
  • Interrupt on input signal change (rising and/or falling edge)
  • Separate programmable interrupts for each input
  • Re-readable outputs
  • Generics for all register values

Software

VxWorks
13Z017-06

MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO

QNX
13Z017-06

MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO

OS-9
13Z017-06

MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO

Documentation