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16Z055_HDLC - Single-Channel HDLC Controller

FPGA IP Core

The HDLC Controller is a single-channel HDLC controller IP core with wishbone interface.

Download data sheet

Main Features

  • FPGA IP Core
  • One HDLC channel
  • Baud rate range from 9600 bit/s up to 1 Mbit/s
  • Wishbone bus interface
16Z055_HDLC Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 1050 typ.
  • Pin count: 6
  • RAM: 16 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
HDLC Functionality
  • One HDLC channel
  • Alternating buffer for data storage (2 kB default memory size)
  • Baud rate range 9600 bit/s up to 1 Mbit/s
  • Full duplex mode
  • Handshake (RTS, CTS, DTR and DSR support in software flow control)
  • CRC: CCITT (x^16 + x^12 + x^5 + 1)
  • Coding: Manchester or NRZI-Manchester

Software

Linux
13Z055-90

Linux native driver (MEN) for 16Z055_HDLC with TCP/PPP support

QNX
13Z055-40

QNX native driver (MEN) for 16Z055_HDLC

Documentation