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16Z076_QSPI - QSPI Interface
FPGA IP Core
The QSPI is a full-duplex, synchronous serial interface for communication with peripherals and other devices.
Main Features
- FPGA IP Core
- Full duplex synchronous serial interface
- Wishbone bus interface
Technical Data
Size
- Logic elements (Altera Cyclone device family): 482 typ.
- Pin count min.: 4
- Pin count max.: 7
- RAM: 4 x 4096 bits
System-Bus Interface
- Wishbone bus interface compliant with Wishbone Specification B.3
- 32-bit data transfer, 33MHz bus frequency
- Supported Wishbone bus cycles
- Single read/write
QSPI Functionality
- Full-duplex, synchronous serial interface
- Buffer size extended to 256 queue entrees
- 33MHz basic frequency
- Additional timer unit
Software
Linux 13MD05-90
The MDIS5 system package includes most standard device drivers for Linux available from MEN.
Windows 13Z010-70
MDIS5 Windows driver (MEN) for 16Z076_QSPI devices
VxWorks 13MD05-60
MDIS5 System (and Device Driver) Package (MEN) for VxWorks. This software package includes most standard device drivers available from MEN.
QNX 13M000-15
MDIS4/2004 system (and device driver) package (MEN) for QNX, source code. This software package includes most standard device drivers available from MEN.
OS-9 13Z010-06
MDIS4/2004 / MDIS5 low-level driver sources (MEN) for 16Z076_QSPI
Documentation
Data Sheets