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16Z079_ANYBUS - Anybus Interface

FPGA IP Core

The 16Z079_ANYBUS interface allows a host application to communicate with an Anybus module.

Download data sheet

Main Features

  • FPGA IP Core
  • Asynchronous parallel interface
  • Serial interface via UART with RX and TX signals
  • Baudrates from 19.2 kbit/s to 625 kbit/s
16Z079_ANYBUS Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 1900
  • Pin count: 40
  • RAM: 1 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles (slave)
    • Single read/write
Interface Functionality
  • Data exchange between host application and Anybus module
  • Parallel interface
    • Asynchronous parallel interface
    • 8-bit bidirectional data bus
    • 14-bit address bus
    • Output enable, chip select and write enable signals
    • Interrupt
  • Serial interface
    • UART with RX and TX signals
    • Supports baudrates: 19.2kbit/s, 57.6kbit/s, 115.2kbit/s and 625kbit/s
  • Configuration
    • 3-bit operating mode register
    • 2-bit module identification register
    • 2-bit module detection register
    • 2-bit general purpose output register
    • 2-bit general purpose input register