Follow Us
F215 - UART, CAN Bus & Digital I/O Interface Board
3U CompactPCI
The F215 is a 3U CompactPCI peripheral card offering different interface configurations for RS-232, RS-422, RS-485 UARTs, CAN bus or binary I/O.
F215 3U CompactPCI Universal Interface Board
Main Features
- 5 interfaces at 8 HP front: 2 UARTs, 2 CAN bus, 1 digital I/O port
- Other function combinations via FPGA IP cores
- For protocols/physical layers like RS232/RS422/RS485, HDLC, InterBus-S, CAN bus, digital I/O
- Physical layers via SA-Adapters
- -40 °C to +85 °C
Technical Data
- Different variations possible through FPGA IP cores and SA-Adapters:
- RS232
- RS422
- RS485
- IBIS master/slave
- CAN bus
- HDLC
- Binary I/O
- The FPGA offers the possibility to add customized I/O functionality. See FPGA.
- Option matrix showing possible IP cores and SA-Adapters (PDF)
- Accessible via onboard connectors
- Physical interface at front panel using SA-Adapters
- Two interfaces for direct onboard connection of SA-Adapters
- Up to six interfaces for connection of SA-Adapters via 10-pin ribbon cable
- Standard factory interface configuration:
- 8 HP front panel with five SA-Adapter cut-outs for
- 2 CAN bus interfaces
- 2 UART interfaces
- 1 binary I/O interface
- No SA-Adapters included by standard; they can be selected as needed
- Standard factory FPGA configuration:
- 16Z029_CAN - CAN controller (controls CAN X1)
- 16Z029_CAN - CAN controller (controls CAN X2)
- 16Z125_UART - UART controller (controls UARTs X3/X4)
- 16Z037_GPIO - GPIO controller (8 I/O lines on X5)
- One status LED to signal FPGA configuration (interfaces ready)
- Three user LEDs, FPGA-controlled by 16Z034_GPIO controller
- 32-bit/33-MHz, 3.3 V V(I/O)
- Compliant with PCI Specification 2.2
- Compliance with CompactPCI Core Specification PICMG 2.0 R3.0
- Peripheral slot
- V(I/O): +3.3 V
- +5 V (-3%/+5%), current depends on mounted SA-Adapters; 200 mA without SA-Adapters
- +3.3 V (-3%/+5%), 150 mA typ.
- Dimensions: conforming to CompactPCI specification for 3U boards
- Front panel: 8 HP with ejector
- For up to five interfaces
- Weight: 175 g (w/o SA-Adapters)
- Temperature range (operation):
- -40..+85°C
- Airflow: min. 1.0 m/s
- Temperature range (storage): -40..+85°C
- Relative humidity (operation): max. 95% non-condensing
- Relative humidity (storage): max. 95% non-condensing
- Altitude: -300 m to +3000 m
- Shock:
- 15 g, 11 ms (EN 60068-2-27)
- 50 m/s², 30 ms (EN 61373)
- Bump: 10 g, 16 ms (EN 60068-2-29)
- Vibration (sinusoidal): 1 g, 10 Hz - 150 Hz (EN 60068-2-6)
- Vibration (function): 1 m/s², 5 Hz - 150 Hz (EN 61373)
- Vibration (lifetime): 7.9 m/s², 5 Hz - 150 Hz (EN 61373)
- Driver software for Windows, Linux, VxWorks, QNX
- Flash update tools for Windows, Linux, VxWorks
- For more information on supported operating system versions and drivers see Software.
FPGA
- FPGA Altera Cyclone III EP3C40
- 39 600 logic elements
- 1134 Kbits total RAM
- For interface functions
- 4 MB external Flash for FPGA configurations
- Connection
- Total available pin count: 64 pins
- Functions available via onboard I/O connectors
- SA-Adapters are used to realize the physical lines.
- Functional updates via software
- MEN offers Flash update tools for different operating systems.
- Option matrix showing possible IP cores and SA-Adapters (PDF)
Options
- Via up to eight SA-Adapters
- Different variations possible through FPGA IP cores and SA-Adapters:
- RS232
- RS422
- RS485
- IBIS master/slave
- CAN bus
- HDLC
- Binary I/O
- InterBus-S
- GPS
- Other physical layers dependent on FPGA configuration
- Option matrix showing possible IP cores and SA-Adapters (PDF)
- 4, 8 or 12 HP front panel dependent on number of SA-Adapters
- 4 HP with 2 onboard SA-Adapters
- 8 HP with 5 SA-Adapters (standard)
- 12 HP with 8 SA-Adapters
- One-piece front panel
Ordering Information
8 HP FPGA-based universal interface for direct connection of 2x CAN (first slot), 2x UART and 1x 8-bit GPIO (second slot) at front as standard FPGA content plus space for user-defined functions, -40..+85°C qualified, interface SA-Adapters to be ordered separately
Software
Linux MDIS5 System (and Device Driver) Package (MEN) for Linux.
This software package includes most standard device drivers available from MEN.
Linux FPGA update tool (MEN)
Linux native driver (MEN) for 16Z055_HDLC with TCP/PPP support
MDIS5 driver (MEN) for 16Z029_CAN (CANopen master)
For this product, the following device drivers are included in the MDIS system package:
MDIS5 low-level driver sources (MEN) for 16Z029_CAN (MSCAN/Layer2)
MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO
Linux native driver (MEN) for 16Z025_UART, 16Z057_UART and 16Z125_UART
Further available tools and drivers:
Windows Windows Embedded Standard 7 BSP
Windows FPGA update tool (MEN)
Windows Installset (MEN) for F215, G215, G229 and MP70S
MDIS5 Windows driver (MEN) for 16Z029_CAN (CANopen master)
VxWorks Further available tools and drivers:
VxWorks FPGA update tool (MEN)
MDIS5 driver (MEN) for 16Z029_CAN (CANopen master)
MDIS5 System (and Device Driver) Package (MEN) for VxWorks. This software package includes most standard device drivers available from MEN.
For this product, the following device drivers are included in the MDIS system package:
MDIS5 low-level driver sources (MEN) for 16Z029_CAN (MSCAN/Layer2)
MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO
VxWorks native driver (MEN) for 16Z025_UART, 16Z057_UART and 16Z125_UART
QNX Further available tools and drivers:
QNX 6.3 native driver (MEN) for 16Z025_UART and 16Z125_UART
QNX 6.4 native driver (MEN) for 16Z025_UART and 16Z125_UART
QNX 6.5 native driver (MEN) for 16Z025_UART and 16Z125_UART
QNX FPGA update tool (MEN)
MDIS5 driver (MEN) for 16Z029_CAN (CANopen master)
MDIS4 system (and device driver) package (MEN) for QNX, source code. This software package includes most standard device drivers available from MEN.
For this product, the following device drivers are included in the MDIS system package:
MDIS5 low-level driver sources (MEN) for 16Z029_CAN (MSCAN/Layer2)
MDIS5 low-level driver sources (MEN) for 16Z034_GPIO, 16Z037_GPIO and 16Z127_GPIO