Log in News & Media | Downloads | Corporate | Careers | Legal Notes
(215) 542-9575

16Z001_SMB - I2C SMBus Controller


The SMBus controller is a bridge between an SMBus and a Wishbone interface. The SMBus features master capabilities, while the Wishbone interface features slave capability.

Download data sheet

Main Features

  • FPGA IP Core
  • SMBus master interface
  • Wishbone slave interface
16Z001_SMB Product Image

Technical Data

  • Logic elements (Altera Cyclone device family): 550 typ.
  • Pin count: 2
  • RAM: 1 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
SMBus Functionality
  • Master operation (revisions 7 and later with Multi-Master support, latest software drivers required!)
  • Quick send byte
  • Quick receive byte
  • Write byte/write word
  • Read byte/read word
  • Block read/block write
  • Read/write I²C message
  • Baud rate generator
  • Interrupt

Ordering Information