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16Z014_PCI - PCI to Wishbone Interface

FPGA IP Core

This core is a PCI to Wishbone bus bridge. It consists of two independent parts, one handling transactions originating on the PCI bus, the other one handling transactions originating on the Wishbone SoC bus.

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Main Features

  • FPGA IP Core
  • PCI to Wishbone bus bridge
  • Wishbone bus interface
16Z014_PCI Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 1400 typ.
  • Pin count min: 50
  • Pin count max: 53
  • RAM: 2 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33/66MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
    • Block read/write
PCI Functionality
  • 32-bit interface
  • PCI 2.2 compliant (33MHz and 66MHz)
  • Separated initiator and target functional blocks
  • Supported initiator commands and functions
    • Memory read/write operations
    • Latency timer
  • Supported target commands and functions
    • Type 0 configuration space header
    • Multifunction device (up to eight devices)
    • Memory read/write and I/O read/write operations
    • Target retry, target disconnect, target abort
    • Delayed or posted writes
    • Delayed and prefetched reads
    • INTA function

Ordering Information

Documentation