Log in/Register News & Media | Downloads | Corporate | Careers | Contact Request
(215) 542-9575

16Z014_PCI - PCI to Wishbone Interface


This core is a PCI to Wishbone bus bridge. It consists of two independent parts, one handling transactions originating on the PCI bus, the other one handling transactions originating on the Wishbone SoC bus.

Download data sheet

Main Features

  • FPGA IP Core
  • PCI to Wishbone bus bridge
  • Wishbone bus interface
16Z014_PCI Product Image

Technical Data

  • Logic elements (Altera Cyclone device family): 1400 typ.
  • Pin count min: 50
  • Pin count max: 53
  • RAM: 2 x 4096 bits
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, 33/66MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
    • Block read/write
PCI Functionality
  • 32-bit interface
  • PCI 2.2 compliant (33MHz and 66MHz)
  • Separated initiator and target functional blocks
  • Supported initiator commands and functions
    • Memory read/write operations
    • Latency timer
  • Supported target commands and functions
    • Type 0 configuration space header
    • Multifunction device (up to eight devices)
    • Memory read/write and I/O read/write operations
    • Target retry, target disconnect, target abort
    • Delayed or posted writes
    • Delayed and prefetched reads
    • INTA function

Ordering Information


Data Sheets
Contact Request! Use this form to get the fastest possible reply.
Please make sure to fill out the complete form, so we can provide quick and specific support.
Your request will be sent to our sales team.

Your information will not be shared!

* required fields

Your Request

Your Contact Data

Please type in the letters and/or numbers that you see in the image on the left (case-sensitive).