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16Z023_IDE - IDE Controller

FPGA IP Core

This universal IDE controller can handle two IDE devices. One primary and one secondary IDE device can be accessed. Only PIO mode 0 is supported. The core does not support DMA.

Download data sheet

Main Features

  • FPGA IP Core
  • Supports primary and secondary IDE device
  • Wishbone bus interface
16Z023_IDE Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 120 typ.
  • Pin count min: 28
  • Pin count max: 34
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 16-bit data transfer, 33MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
IDE Functionality
  • PIO mode 0
  • Supports primary and secondary device
  • Also available as non-hot-swappable variant (16Z023_IDENHS)

Ordering Information

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