16Z024_SRAM - SRAM Controller
FPGA IP Core
The SRAM controller handles access to static RAMs up to a size of 4 MB. The SRAM address space has a size of 4MB, so a dedicated Base Address Register is used for the SRAM memory space.
- Logic elements (Altera Cyclone device family): 280 typ. (101 typ. for 16Z024-02)
- Pin count min: 26
- Pin count max: 60
- Wishbone bus interface compliant with Wishbone Specification B.3
- 32-bit data transfer, 33MHz bus frequency (up to 133 MHz for 16Z024-02)
- Supported Wishbone bus cycles
- Single read/write
- Access to memory devices (SRAM, Flash ROM)
- Up to 4 MB SRAM
- 8-bit/16-bit or 32-bit data width
- Variable memory configuration
The MDIS5 system package includes most standard device drivers for Linux available from MEN.
MDIS4/2004 / MDIS5 Windows driver (MEN) for 16Z024_SRAM
MDIS5 System (and Device Driver) Package (MEN) for VxWorks. This software package includes most standard device drivers available from MEN.
MDIS4/2004 system (and device driver) package (MEN) for QNX, source code. This software package includes most standard device drivers available from MEN.
MDIS4/2004 / MDIS5 low-level driver sources (MEN) for 16Z024_SRAM