Log in News & Media | Downloads | Corporate | Careers | Legal Notes
(215) 542-9575
sales@menmicro.com

16Z043_SDRAM - SDRAM Controller

FPGA IP Core

This product is an SDRAM controller for FPGA to SDRAM interfaces. The main functionality is to connect the Wishbone bus to SDRAM memory, with up to 133 MHz clock frequency. Single and burst transactions are supported.

Download data sheet

Main Features

  • FPGA IP Core
  • Supports up to 133 MHz clock frequency
  • Single and burst transactions
  • Wishbone bus interface
16Z043_SDRAM Product Image

Technical Data

Size
  • Logic elements (Altera Cyclone device family): 1200 (16Z043-00) or ~1100 (16Z043-01)
  • Pin count min: 38 for 16Z043-00, 43 for 16Z043-01
  • Pin count max: 57 for 16Z043-00, 43 for 16Z043-01
  • RAM: 5 x M4K (Cyclone I and II) or 5 x M9K (Cyclone III)
  • (3 x M4K and 3 x M9K for later revisions of 16Z043-00)
System-Bus Interface
  • Wishbone bus interface compliant with Wishbone Specification B.3
  • 32-bit data transfer, up to 133MHz bus frequency
  • Supported Wishbone bus cycles
    • Single read/write
    • Burst read/write
  • Second Wishbone interface for enhanced data throughput
  • Flexible FIFO depth for best system integration
SDRAM Functionality
  • SDR SDRAM data width 16 or 32 bits (16Z043-00)
  • DDR2 SDRAM data width 16 bits (16Z043-01)
  • Variable CAS latency
  • Up to 133 MHz clock rate
  • Refresh counter

Ordering Information