16Z058_SRAM - SRAM over SPI Interface
FPGA IP Core
The SRAM over SPI Interface is a normal indirectly addressable memory interface on the Wishbone bus side and connects to the SRAM via an SPI interface.
- Logic elements (Altera Cyclone device family): 245 typ.
- Pin count: 4
- Wishbone bus interface compliant with Wishbone Specification B.3
- 32-bit data transfer, 33MHz bus frequency
- Supported Wishbone bus cycles
- Single read/write
- Indirect addressing
- SRAM over SPI interface
- Clock reads and writes
- Automatic address incrementation on multiple read or write cycles